Electronic components can fail for many different reasons; therefore, components can benefit from failure management. Failures can be caused by excess temperature, excess voltage, ionizing radiation, mechanical shock or stress, and many other causes. For example, in semiconductor devices, problems in the device package may cause failures such as contamination, mechanical stress, or short circuits. Often, failures occur near the beginning or ending of the lifetime of a device. Also, in semiconductor devices, parasitic structures can be a source of failures such as delays. For example, dysfunctional vias can be a common source of unwanted serial resistance on chips and can cause propagation delays. In general, semiconductor failures are often electrothermal. Locally increased temperatures can lead to immediate failure by melting metallisation layers or the semiconductor, or by changing structures of the semiconductor. As it is apparent, electronic components can fail for many different reasons; and consequently, limit the life of a component. Thus, it is advantageous to include failure management in electronic components.
A 3D IC is an integrated circuit built by stacking silicon dies and interconnecting them vertically so that a combination of the dies is a single device. With a 3D IC, electrical paths through the device can be shortened by its vertical layout, which creates a device that can be faster and has a smaller footprint than similar ICs arranged side-by-side. 3D ICs can be generally grouped into 3D SICs, which refers to stacked ICs with through-silicon via interconnects (TSVs), and monolithic 3D ICs, which are generated using fabrication processes to realize 3D interconnects at the local levels of the on-chip wiring hierarchy as set forth by the International Technology Roadmap for Semiconductors (ITRS). Using the fabrication processes to realize the 3D interconnects can produce direct vertical interconnects between device layers. Monolithic 3D ICs are built in layers on a single wafer that is diced into separate 3D ICs.
3D SICs can be produced by three known general methods: a die-to-die, die-to-wafer, or a wafer-to-wafer method. In a die-to-die method, electronic components are generated on multiple dies. Then, the dies are aligned and bonded. A benefit of a die-to-die method is that each die can be tested before aligned and bonded with another die. In a die-to-wafer method, electronic components are generated on multiple wafers. One of the wafers can be diced and then aligned and bonded on to die sites of another wafer, accordingly. In a wafer-to-wafer method, electronic components are generated on multiple wafers, which are then aligned, bonded, and diced into separate 3D ICs.
A TSV is a vertical electrical connection that can pass through a die. TSVs can be a central part to increasing performance in 3D packages and 3D ICs. With TSVs, compared to alternatives for connecting stacked chips, the interconnect and device density can be substantially higher, and the length of the connections can be shorter.